1. Field of the Invention
The present invention relates to a semiconductor device, an electro-optic device in which the semiconductor device is used as a transistor array substrate, and an electronic instrument in which the electro-optic device is used.
2. Description of Related Art
Currently, of various kinds of electro-optic devices, such as an active matrix type liquid crystal device that uses a thin film transistor (TFT) as a pixel switching non-linear element, are used in various kinds of electronic instruments, such as direct view display devices and projection display devices. In the electro-optic device, between a TFT array substrate (transistor array substrate/semiconductor device) on which pixel switching TFTs and pixel electrodes are formed in matrix corresponding to positions where data lines intersect scanning lines and an opposite substrate thereon an opposite electrode is formed, a liquid crystal as an electro-optic material is retained. Furthermore, on the TFT array substrate, in some cases, various kinds of driving circuits are formed by use of complementary TFTs.
Furthermore, as shown in FIGS. 24 through 26, on the TFT array substrate, an electrostatic protection circuit that protects a driving circuit or the like from a surge voltage caused by static electricity is formed.
FIG. 24 is an equivalent circuit diagram showing a layout of an electrostatic protection circuit and the surroundings thereof in a TFT array substrate that is used in an existing liquid crystal device. FIG. 25 is a plan view showing a layout of an electrostatic protection circuit and the surroundings thereof in a TFT array substrate that is used in an existing liquid crystal device. FIG. 26 is a cross sectional view taken when a TFT that forms and electrostatic protection circuit and intersections of wirings are cut by a D-D′ line, a D1-D1′ line and a D2-D2′ line of FIG. 25 in a TFT array substrate that is used in an existing liquid crystal device.
As shown in FIGS. 24 through 26, in a TFT array substrate 10, along a substrate side 111, a signal input terminal 670 receives various kinds of signals that are supplied from the outside, a terminal 710 receives a high potential VDDX that is supplied from the outside, and a terminal 720 receives a low potential VSSX that is supplied from the outside are arranged. From these terminals 670, 710 and 720, a signal input line 67, a high potential line 71 and a low potential line 72, respectively, are extended up to a data line driving circuit 101. Furthermore, to the middle of the signal input line 67 an electrostatic protection circuit 5 is electrically connected, and in the electrostatic protection circuit 5, in order that a p-channel TFT 80 and a n-channel TFT 90 each may work as a normally-off diode, a gate electrode 65 and a source region 82 are fixed at a high potential VDDX, and a gate electrode 66 and a source region 92 are fixed at a low potential VSSX.
The high potential line 71 extends in a direction that intersects the signal input line 67 at a region more toward a substrate side 112 than a region where the signal input terminal 670 and the electrostatic protection circuit 5 are formed, and extends therefrom to a source region 82 of the p-channel TFT 80 of the electrostatic protection circuit 5. On the other hand, the low voltage line 72 goes through between a region where the signal input terminal 670 is formed and a region where the electrostatic protection circuit 5 is formed and extends toward a direction that intersects the signal input line 67, and extends therefrom to the electrostatic protection circuit 5.
In the above, since each of the wirings is formed in a multi-layered wiring structure, even when intersecting the others, between layers of the respective wirings an interlayer insulating film 4 is interposed. In other words, while body portions of the high potential line 71, the low potential line 72 and the signal input line 67 are formed of wirings on a top layer side than the interlayer insulating film 4, these body portions are partially intercepted at intersection portions 672, 717 and 729, and an electrical connection at the intercepted portions is established by going through a substrate wiring 3c in the same layer with the gate electrodes 65 and 66, and contact holes 718 and 719.
In the TFT array substrate 10 thus configured, even when a surge voltage due to static electricity enters from the signal input terminal 670, the surge voltage is expected to be absorbed by the electrostatic protection circuit 5 before entering the data line driving circuit 101. However, in the existing TFT array substrate 10, in the middle portion from the signal input terminal 670 to the electrostatic protection circuit 5, an intersection portion 729 between the signal input line 67 and the low potential line 72 is present. Accordingly, there can be a problem in that when a surge voltage enters from the signal input terminal 670, owing to the surge voltage, the intersection portion 729 between the signal input line 67 and the low potential line 72 is heated, and because of Joule heat thereof the signal input line 67 or the low potential line 72 is disconnected.